In current state of the art the use of semiconductor-on-insulator (SOI) wafers or substrates is widely known for the integration of semiconductor devices as it has a superior scalability and good performance. However the use of SOI wafers also involves different drawbacks. SOI wafers are very expensive. Moreover, due to the buried oxide layer, many devices cannot be built easily on a SOI substrate. For sub-32 nm technology node, the buried oxide layer thickness is less than 20 nm. The integration of, for example, periphery devices on SOI substrates may form a problem due to the intrinsically low breakdown voltage in thin-body SOI.
There is a need for hybrid semiconductor substrates whereupon both SOI devices and bulk semiconductor devices may be integrated together.
For NAND flash memory devices, the physical scaling as well as the electrical scaling has become more challenging with each technology node.
In state-of-the-art NAND flash memory devices, the ONO (oxide-nitride-oxide) interpoly dielectric runs along the sidewalls of the floating gate in order to provide a large capacitance between floating gate and control gate and therefore a large coupling ratio. As the IPD layer is present twice in a floating gate flash device, scaling of thickness of the IPD layer becomes a limiting factor for flash scaling below a 2X generation technology node. To achieve good data retention, the thickness of the IPD layer is limited to about 12 to 15 nm using state-of-the art materials, which means already 24 to 30 nm pitch size at least, as it is still necessary to add the thickness of the floating gate and the control gate.
FIG. 1 shows a schematic representation of a state-of-the-art floating gate memory device on a substrate 1, comprising floating gate structures 2, isolation areas 3, interpoly dielectric layer 4, tunnel oxide layers 5 and control gate 6. It is seen that the scaling of the pitch P of floating gate memory device becomes a great challenge as it is necessary within the pitch P to have room for the floating gate (FG) 2, for an interpoly dielectric (IPD) layer 4, for a control gate (CG) 6 and for an interpoly dielectric (IPD) layer 4 (again). With the materials currently used for the IPD layer, i.e. ONO or AlO-based dielectric stack, the thickness of the IPD layer is limited to about 12 to 15 nm in order to achieve good data retention for the memory device. When scaling to smaller thickness, the electrical properties of the materials currently used for the IPD layer are not good enough anymore since smaller thickness causes increased leakage and bad performance of the device.
In order to improve the quality and scalability of the IPD layer there is a need for other materials. One possibility is the use of monocrystalline silicon (c-Si) for the floating gate which gives the opportunity to use thermal oxide grown on the c-Si floating gate as IPD layer. The concept of using a monocrystalline floating gate and thereupon a thermally grown oxide as IPD layer has been reported in the JP patent JP2668707 B2.
A possibility to integrate a c-Si floating gate is by using a semiconductor-on-insulator (SOI) substrate. The top silicon layer of the SOI substrate is then used as floating gate layer, which implies that the buried oxide of the SOI substrate is used as tunnel dielectric layer and the underlying bulk silicon is used as transistor channel.
However, as stated above, SOI wafers are expensive and the buried oxide layer of an SOI wafer is too thick to be used as tunnel oxide, thus it needs further thinning.
There is a need for floating gate memory devices with a good data retention and electrical performance, which are scalable below 3X generation technology node, and even scalable below 2X generation technology node.